Next, the simulation of a component with feedback is traced. This trace will demonstrate why it is necessary to increment the local time at the top of the while loop and why it is necessary for the Wire constructor to place an X at the initial time in the wire queue. The initial configuration of the circuit and its corresponding wires is shown in Figure A.3. Note that the input wires have some empty time slots. This means that the signal at that time is the same as the signal that was before it. For example, in ci1, the signal at time t = 1 is the same as the signal at time t = 0, that is, L. It was necessary to space out the input signals in order to avoid resonance during the simulation of the RS-latch.
Figure A.3: RS-Latch Before Simulation
As was the case with the three-input AND gate, the RS-latch receives a message telling it to simulate. The RS-latch, being at its initial time, has inputs ready waiting for it. It then increments its local time to zero and sends simulate() messages to all its subcomponents via the descend() method.
At this point, it is assumed that nand2a is the first component to receive the simulate() message. It examines its two input wires, ci1 and co2 and discovers that they both have inputs waiting at times corresponding to its local initial time. Note that if the Wire constructor had not placed an initial X input on the co2 wire, the simulation would essentially stop at this point producing no output. The nand2a gate increases its local time to zero and sends its processed result (X) to the Q output port at time t = 0. Q takes this signal and sends it to the wire co1. Since co1 is not connected to anything, control is passed back to Q. Q then sends simulate() messages to all the components in its fan-out. Control is passed to nand2b since it is the only element in the fan-out.
Upon receiving control, nand2b discovers that its input signals are ready from wires ci2 and co1. It increments its local time to zero and sends an X signal to Qb at time t = 0. Upon receipt of this signal, Qb sends the signal to co2 which passes control back to Qb. Qb then sends the simulate message to all the components in its fan-out; namely and2a.
It is at this point that we realize the importance of increasing a component's local time immediately after determining whether all its inputs are ready. Had we postponed the incrementing of the local time until after the process() method, nand2a would still be at its initial local time, causing it to re-read the signals it read previously, hence resulting in an infinite loop. However, because nand2a previously incremented its time to zero, it is able to look ahead at the next set of inputs. Upon discovering that more inputs are available, the local time is increased to one. The L from ci1 and the X from co2 are nanded together to produce H which is sent to Q at time t = 1.
After this signal is sent to the wire co1, Q sends a simulate() message to nand2b, at which point nand2b increments its local time to one, reads the H and the X from ci2 and co1 respectively and sends the resulting X to Qb at time t = 1.
After placing this signal in the wire, control is again passed to nand2a which determines that all its inputs are ready and therefore increases its local time to two. An L signal is read from ci1 (unchanged from the previous time) and is processed with the X read from co2. The resulting H signal is sent to Q at time t = 2.
After Q places the signal on the wire, control is passed yet again to nand2b. All its inputs are ready, so it increments its local time to two and processes the H signal from ci2 and the H signals from co1 to produce an L output at time t = 2.
This method of passing control back and forth continues until all the inputs on ci1 and ci2 have been exhausted. Then, like in the three-input AND gate, the RS-latch's local time catches up to the local time of its subcomponents. All the messages which are sent to the two NAND gates are essentially ignored and the simulation ends when the local time of the RS-latch exceeds the time of the last input on the wire. In this particular example, the simulation will terminate when the local time of the RS-latch reaches seven.
A diagram illustrating the state of the RS-latch after the simulation is shown in Figure A.4.
Figure A.4: RS-Latch After Simulation
The reader can easily verify that this model exhibits the characteristics of an RS-latch, including the ``race condition,'' when the appropriate inputs are provided.