Local time contributes to the preservation of the autonomy of components during a simulation. However, in any simulation, components still require some means of communication with other components. Ideally, the method of interaction between components should be intuitive and should not introduce bottlenecks into the simulation by relying upon the presence of a global mechanism. For this reason, distributed event queues were introduced to help maintain the autonomy of a component by encouraging interactions amongst adjacent components only. As with local time, distributed event queues are also amenable to the hierarchical representations of circuits.
Figure 4.3 shows a simulation in progress which employs distributed event queues. The circuit is identical to that presented in Figure 4.1 but the global event queue has been eliminated. Instead, the event queue has essentially been distributed throughout the circuit representation. These distributed queues are analogous to wires in actual circuits, in that they serve as the conduits in which signals pass from one component to other components in its fan-out thereby connecting components together.
Figure 4.3: Digital Simulation Using Distributed Event Queues
In addition, these distributed queues also maintain a history of the events (or signals) which have travelled along them during the course of the simulation. Hence, when a component is being simulated, it may query its input wires (via its ports) to obtain the value of the signal which occurred at local time of the component. If the input signals are not available in the queue at the requested time, then the component will not be permitted to simulate. As demonstrated by the figure, it is necessary for the event queues to maintain a history of their signal values since the local times of the components to which they are attached may vary significantly.
The following subsections describe how distributed event queues serve the dual function of expressing connectivity and facilitating the simulation of a circuit. Details with respect to circuit representation and class design strategies will be discussed in depth.