The traditional approach towards gate-level simulation employs a global event queue which communicates directly with every component that participates in the simulation . The queue is typically implemented as a linked list where each node represents a moment in time. Each node of the event queue contains a pointer to a chain of events which have been scheduled by the simulator to occur at that particular time. These events often consist of a pointer to the component which is to be simulated and an indication of what action the component must take.
As events are processed and components are simulated, subsequent events are scheduled further ahead in time in the event queue. This scheduling of events represents how signals are propagated within the circuit -- the global event queue is responsible for caching the outputs of a component and then feeding it to the corresponding fan-out components when the appropriate time node of the event queue has been reached during the simulation. The simulation runs until the event queue has been exhausted or until the time alloted for the simulation has expired. Figure 4.1 shows the relationship between a global event queue and the circuit that it is simulating.
Figure 4.1: Digital Simulation Using a Global Event Queue
As can be seen from the figure, this method of simulation partitions the problem into two separate entities. The global event queue maintains all the simulation information; the circuit representation contains all the connectivity details. It will be demonstrated in subsequent sections how these two separate entities can be effectively merged into a distributed structure which maps naturally onto the wires of the circuit domain.