"Timed Petri net models of shared-memory bus-based multiprocessors"

Zuberek, W.M.

Journal of Computers and Communications, vol.6, no.10, pp.1-14, 2018 (DOI 10.4236/jcc.2018.610001).

Abstract:

In shared--memory bus--based multiprocessors, when the number of processors grows, the processors spend an increasing amount of time waiting for access to the bus (and shared memory). This contention reduces the performance of processors and imposes a limitation of the number of processors that can be used efficiently in bus--based systems. Since the multiprocessor's performance depends upon many parameters which affect the performance in different ways, timed Petri nets are used to model shared--memory bus--based multiprocessors at the instruction execution level, and the developed models are used to study how the performance of processors changes with the number of processors in the system. The results illustrate very well the restriction on the number of processors imposed by the shared bus. All performance characteristics presented in this paper are obtained by discrete-event simulation of Petri net models.

Keywords:

shared--memory multiprocessors, bus--based multiprocessors, timed Petri nets, discrete--event simulation.

References:

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