This appendix will trace through some sample simulations
to demonstrate how the algorithm works. In the following
diagrams, the symbol `*' represents the initial
time. To prevent confusion, the time when
signals occur will be represented as numbers beneath
the signal in the wire queue. The signals themselves will
be represented as H, L and X, representing
high, low and unknown respectively. The time delay of the
encapsulated subcomponents is represented by a number inside
the component's box. The time delay for the enclosing
component depends upon the delay for each of its encapsulated
subcomponents and their connectivity.
The local time for all components at the start of the
simulation is set at `*', so when the local time
of a component is first incremented, it becomes zero.
For simplicity, we assume inputs to be available at integer times
