Distributed-memory multiprocessor architectures are composed of a number of processors, each with its (local) memory, and an interconnection network. Instruction-level multithreading is one of techniques which tolerate long memory latencies and unpredictable synchronization delays in such systems. In block multithreading, the (current) sequence of instructions (i.e., the current thread) is executed until a long-latency operation is encountered and the context switching takes place, i.e., the current thread is suspended and the processor switches to another "ready" thread provided such a thread is available. In interleaved (or fine-grain) multithreading, several threads issue instructions cyclically (so the thread change occurs after each instruction).
Because of very simple representation of concurrency and synchronization, timed Petri net models seem to be well suited to modeling and evaluation of such architectures.
Specific projects in this area include:
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Copyright by W.M. Zuberek. All rights reserved.
Revised: 2004.07.25 : :5760