Selected other publications:

• "Compatibility of software components - modeling and verification" (with D.C. Craig); Proc. Int. Conf. on Dependability of Computer Systems (DepCoS'06), Szklarska Poreba, Poland, pp.11-18, May 2006.
• "Speedup of distributed iterative solvers of large sparse systems of linear equations" (with T.D.P. Perera); WSEAS Transactions on Mathematics, vol.4, no.3, pp.281-288, 2005.
• "Modeling and verification of compatibility of component composition" (with D.C. Craig); Proc. 3-rd Workshop on Modeling of Objects, Components, and Agents (MOCA'04), Aarhus, Denmark, pp.117-130, October 2004.
• "Cluster tools with chamber revisiting - modeling and analysis using timed Petri nets"; IEEE Transactions on Semiconductor Manufacturing, vol.17, no.3, pp.333-344, 2004.
• "Modeling and analysis of dual block multithreading"; in Applying Formal Methods: Testing, Performance, and M/E-Commerce (Lecture Notes in Computer Science 3236), Proc. European Performance Evaluation Workshop (EPEW'04) of the 24-th IFIP WG 6.1 Int. Conf. on Formal Techniques for Networked and Distributed Systems (FORTE'04), Toledo, Spain, pp.209-219, September 2004.
• "On the speedup of distributed linear solvers" (with T.D.P. Perera); Proc. 5-th EUROSIM Congress on Modeling and Simulation (Special Session on Modeling and Simulation of Distributed Systems and Networks), Marne la Vallee, France, pp.222-223, September 2004.
• "Enhanced interleaved multithreaded multiprocessors and their performance analysis"; Proc. 4-th Int. Conf. on Application of Concurrency to System Design (ACSD-04), Hamilton, Canada, pp.7-15, June 2004.
• "Estimation of the speedup of distributed applications"; Proc. Int. Conf. on Advances in the Internet, Processing, Systems, and Interdisciplinary Research (IPSI'04), Studenica Monastery, Serbia, June 2004.
• "Petri nets and timed Petri nets in modeling and analysis of concurrent systems"; Record of the Research Forum 2003 (organized on the 25-th Anniversary of the Department, November 13, 2003), Department of Computer Science, Memorial University, St.John's, Canada A1B 3X5, pp.46-73.
• "Performance analysis of fine-grain multithreaded multiprocessors"; International Journal of Simulation, vol.4, no.3-4, pp.12-20, 2003.
• "Structural methods in performance analysis of discrete-event systems"; Proc. 9-th IEEE Int. Conf. on Methods and Models in Automation and Robotics, Miedzyzdroje, Poland, vol.2, pp.877-882, August 2003.
• "Performance equivalent multiprocessor systems"; Proc. ICALP'03 Workshop on Stochastic Petri Nets and Related Formalisms, Eindhoven, Holland, pp.123-136, June 2003.
• "Systematic construction and performance analysis of cluster tools using timed Petri net models"; 14 Congresso Brasileiro de Automatica (14-th Brazilian Automation Conference) - Petri Net Workshop, Natal, Brazil, September 2-5, 2002.
• "Performance study of distributed generation of state spaces using colored Petri nets"; Int. Workshop on Practical Use of CPNs and Design/CPN (CPN'02), Aarhus, Denmark, pp.81-98, August 2002.
• "Performance equivalence in the simulation of multiprocessor systems"; International Journal of Simulation, vol.3, no.1-2, pp.80-88, 2002.
• "Interconnecting networks and the performance of multithreaded multiprocessors"; Proc. SSGRR Summer Conf. on Infrastructure for e-Business, e-Education, e-Science and e-Medicine; L'Aquila, Italy, August 2002.
• "Analysis of performance bottlenecks in multithreaded multiprocessor systems"; Fundamenta Informaticae, vol.50, no.2, pp.223-241, 2002.
• "Performance balancing of fine-grain multithreaded distributed-memory multiprocessors"; Proc. High Performance Computing Symposium (HPC'02), San Diego, CA, pp.129-134, April 2002.
• "Approximate simulation of distributed-memory multithreaded multiprocessors" ; Proc. 35-th Annual Simulation Symposium, San Diego, CA, pp.107-115, April 2002.
• "Timed Petri nets in modeling and analysis of cluster tools"; IEEE Transactions on Robotics and Automation, vol.17, no.5, pp.562-575, 2001.
• "Petri net modeling and performance analysis of cluster tools with chamber revisiting"; Proc. IEEE Int. Conf. on Emerging Technologies and Factory Automation (ETFA'01), Juan-les-Pins, France, pp.105-112, October 2001.
• "Performance analysis of enhanced fine-grain multithreaded distributed-memory systems"; Proc. IEEE Conf. on Systems, Man, and Cybernetics (SMC'01), Tucson, AZ, pp.1101-1106, October 2001.
• "Timed Petri net models of multi-robot cluster tools"; Proc. IEEE Conf. on Systems, Man, and Cybernetics (SMC'01), Tucson, AZ, pp.2729-2734, October 2001.
• "Analysis of performance limitations in multithreaded multiprocessor architectures"; Proc. 2-nd Int. Conf. on Application of Concurrency to System Design, Newcastle, UK, pp.43-52, June 2001.
• "Space partitioning and speedup in distributed generation of state spaces" (with I. Rada); Proc. 15-th European Simulation Multiconference (ESIM'01), Prague, Czech Republic, pp.554-559, June 2001.
• "Distributed generation of state space for timed Petri nets" (with I. Rada); Proc. High Performance Computing Symposium 2001 (HPC'01), Seattle, WA, pp.219-227, April 2001.
• "Modeling and analysis of distributed state space generation for timed Petri nets" (with I. Rada); Proc. 34-th Annual Simulation Symposium (SS-2001), Seattle, WA, pp.93-98, April 2001.
• "Hierarchical analysis of manufacturing systems using Petri nets"; Proc. IEEE Int. Conf. on Systems, Man, and Cybernetics (SMC'2000), Nashville, TN, vol.4, pp.3021-3026, October 2000.
• "Timed Petri net models of cluster tools"; Proc. IEEE Int. Conf. on Systems, Man, and Cybernetics (SMC'2000), Nashville, TN, vol.4, pp.3063-3068, October 2000.
• "Analysis of pipeline stall effects in block multithreaded multiprocessors"; Proc. 16-th Performance Engineering Workshop, Durham, UK, pp.187-198, July 2000.
• "Petri nets in hierarchical modeling of manufacturing systems"; Proc. IFAC Conf. on Control System Design (CSD'2000), Bratislava, Slovakia, pp.287-292, June 2000.
• "Performance comparison of fine-grain and block multithreaded architectures"; Proc. High Performance Computing Symposium 2000, Washington, DC, pp.383-388, April 2000.
• "Event-driven simulation of timed Petri net models"; Proc. 33-rd Annual Simulation Symposium (SS-2000), Washington, DC, pp.91-99, April 2000.
• "Performance modeling of multithreaded distributed memory architectures"; in: "Hardware Design and Petri Nets", pp.311-331, Kluwer Academic Publ. 2000.
• "Petri net models of process synchronization mechanisms"; Proc. IEEE Int. Conf. on Systems, Man, and Cybernetics (SMC'99), Tokyo, Japan, vol.1, pp.841-847, October 1999.
• "Hierarchical derivation of Petri net models of composite schedules for manufacturing cells"; Proc. IEEE Int. Conf. on Systems, Man, and Cybernetics (SMC'99), Tokyo, Japan, vol.3, pp.775-780, October 1999.
• "Timed Petri net models of ATM LANs" (with M. Reid); in "Application of Petri Nets to Communication Networks" (Lecture Notes in Computer Science 1605), pp.150-175, Springer-Verlag 1999.
• "Stepwise refinements of net models and their place invariants"; Proc. 8-th Int. Workshop on Petri Nets and Performance Models (PNPM'99), Zaragoza, Spain, pp.92-101, September 1999.
• "Timed Petri nets in modeling and analysis of simple schedules for manufacturing cells" (with W. Kubiak); Journal of Computers and Mathematics with Applications, vol.37, no.11-12, pp.191-206, 1999.
• "Approximate performance evaluation of multithreaded distributed memory architectures"; Proc. 15-th Performance Engineering Workshop, Bristol, UK, pp.81-92, July 1999.
• "Performance modeling of multithreaded distributed memory architectures"; 20-th Int. Conf. on Application and Theory of Petri Nets: 2-nd Workshop on Hardware Design and Petri Nets (HWPN'99), Williamsburg, VA, pp.63-82, June 1999.
• "Hierarchical modeling of manufacturing systems"; Mechanical Engineering, vol.3, no.2-3, pp.69-86, 1998.
• "Performance bounds for distributed memory multithreaded architectures" (with R. Govindarajan); Proc. IEEE Int. Conf. on Systems, Man, and Cybernetics (SMC'98), San Diego, CA, pp.232-237, October 1998.
• "Timed Petri nets and performance evaluation of systems"; Proc. IEEE Int. Conf. on Systems, Man, and Cybernetics (SMC'98), San Diego, CA, pp.278-283, October 1998.
• "Methods and tools for characterization of semiconductor device models" (with A. Konczykowska); Proc. 5-th IEEE Int. Conf. on Electronics, Circuits and Systems, Lisboa, Portugal, vol.3, pp.85-88, September 1998.
• "Hierarchical derivation of schedules for manufacturing cells"; Proc. IFAC Symp. on Information Control Problems in Manufacturing (INCOM'98), Nancy/Metz, France, vol.2, pp.423-428, June 1998.
• "Timed colored Petri net models of distributed memory multithreaded multiprocessors" (with R. Govindarajan, F. Suciu); Proc. Workshop on Practical Use of Colored Petri Nets and Design/CPN, Aarhus, Denmark, pp.253-270, June 1998.
• "Symbolic methods in semiconductor parameter extraction" (with A. Konczykowska); in "Symbolic analysis techniques - applications to analog design automation", pp.291-311, IEEE Press 1998.
• "Performance balancing in multithreaded multiprocessor systems" (with R. Govindarajan); Proc. 4-th Australasian Conf. on Parallel and Real-Time Systems (PART'97), Newcastle, Australia, pp.15-26, September 1997.
• "Timed Petri net models of multithreaded multiprocessor architectures" (with R. Govindarajan, F. Suciu); Proc. 7-th Int. Workshop on Petri Nets and Performance Models (PNPM'97), San Malo, France, pp.153-162, July 1997.
• "High-performance computing initiative at MUN: CS-6728 experience" (with E. Baddour); Proc. 5-th Int. Conf. on Applications of High-Performance Computers in Engineering, Santiago de Campostela, Spain, pp.147-156, July 1997.
• "Modular circuit simulation with integrated applications"; Computers and Electrical Engineering, vol.22, no.2, pp.85-101, 1996.
• "Hierarchies of place/transition refinements in Petri nets" (with I. Bluemke); Proc. IEEE Conf. on Emerging Technologies and Factory Automation (ETFA-96), Lihue, Kauai HI, pp.355-360, November 1996.
• "Composite schedules of manufacturing cells and their timed Petri net models"; Proc. IEEE Int. Conf. on Systems, Man, and Cybernetics (SMC'96), Beijing, China, pp.2990-2995, October 1996.
• "Optimal schedules of manufacturing cells - modeling and analysis using timed Petri nets"; Proc. IEEE Int. Symp. on Industrial Electronics (ISIE-96), Warsaw, Poland, pp.1055-1060, June 1996.
• "Schedules of flexible manufacturing cells and their timed colored Petri net models"; Proc. IEEE Int. Conf. on Systems, Man and Cybernetics, Vancouver, BC, pp.2142-2147, October 1995.
• "Application of timed Petri nets to modeling the schedules of manufacturing cells"; Proc. INRIA/IEEE Conf. on Emerging Technologies and Factory Automation, Paris, France, vol.2, pp.311-322, October 1995.
• "Improving performance of parameter extractors through symbolic simulation" (with A. Konczykowska); Proc. IEEE Int. Symp. on Industrial Electronics (ISIE-95), Athens, Greece, pp.445-450, July 1995.
• "Function evaluation in symbolic analysis" (with A. Konczykowska); Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS-95), Seattle, WA, pp.2217-2220, June 1995.
• "Simulation-based parameter extraction - its implementation and some applications" (with A. Konczykowska, C. Algani, H. Wang, J. Dangla); IEE Proc. Circuits, Devices and Systems, vol.141, no.2, pp.129-134, 1994.
• "Self-heating effects and mixed-domain simulation in parameter extraction" (with A. Konczykowska); Proc. First Int. Conf. on Electronics, Circuits and Systems, 19-22 December 1994, Cairo, Egypt.
• "Throughput analysis of manufacturing cells using timed Petri nets" (with W. Kubiak); Proc. IEEE Int. Conf. on Systems, Man and Cybernetics, San Antonio, TX, pp.1328-1333, October 1994.
• "Modeling simple schedules of manufacturing cells using timed Petri nets" (with W. Kubiak); Proc. Int. Workshop on Intelligent Systems and Innovative Computations, Tokyo, Japan, pp.38-47, August 1994.
• "An approach to integrated numerical and symbolic circuit analysis" (with A. Konczykowska); Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS-94), London, England, pp.33-36, June 1994.
• "Parameter extraction of semiconductor devices - electrical models using symbolic approach" (with A. Konczykowska, P. Rozes); Alta Frequenza, vol.5, no.6, pp.3-5, 1993.
• "Throughput analysis in timed colored Petri nets"; Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS'93), Chicago, IL, pp.2721-2724, 1993.
• "Timed Petri net models of flexible manufacturing cells"; (with W. Kubiak); Proc. 36-th Midwest Symposium on Circuits and Systems, Detroit, MI, pp.922-925.
• "Flexible circuit simulation with mixed-domain and mixed-mode applications"; Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS'92), San Diego, CA, pp.81-84, 1992.
• "Temperature dependence of DC currents in HBT" (with H. Wang, C. Algani, A. Konczykowska); Proc. IEEE Int. Microwave Symp. (MTT-S'92), Albuquerque, NM, pp.731-734, 1992.
• "Throughput analysis in timed Petri nets"; Proc. 35-th Midwest Symposium on Circuits and Systems, Washington, DC, pp.1576-1580, 1992.
• "Timed Petri nets - definitions, properties and applications"; Microelectronics and Reliability (Special Issue on Petri Nets and Related Graph Models), vol.31, no.4, pp.627-644, 1991.
• "Nonlinear circuit optimization and component model characterization - simulated annealing and SPICE-PAC coupling" (with G. Berthiau, F. Durbin, J. Haussy, P. Siarry); Annales des Telecommunications, vol.46, no.3/4, pp.205-215, 1991.
• "Parameter extraction with the FIT-2 program" (with A. Konczykowska, J. Dangla); Proc. European Conf. on Circuit Theory and Design, Copenhagen, Denmark, pp.762-771, 1991.
• "Mixed-mode, analog-digital simulation using SPICE-like circuit analysis programs" (with P.E. Allen); IEE Journal of Semicustom ICs, vol.8, no.1, pp.17-29, 1990.
• "Flexible time-domain analysis in the SPICE-PAC package"; Transactions of the Society for Computer Simulation, vol.7, no.1, pp.1-19, 1990.
• "Integrated circuit performance optimization with simulated annealing algorithm and SPICE-PAC circuit simulator" (with F. Durbin, J, Haussy, G. Berthiau, P.Siarry); Proc. European Conference on Application Specific Integrated Circuits (EURO ASIC'90), Paris, France, pp.408-412, 1990.
• "TEGESED, a tool for efficient technological and geometrical characterization of semiconductor devices" (with A. Konczykowska); Proc. European Design Automation Conf. (EDAC'90), Glasgow, Scotland, 1990.
• "Software interfaces for integrated simulation applications"; Proc. 9-th Annual Int. Phoenix Conf. on Computers and Communications (PCCC'90), Scottsdale, AZ, pp.832-839, 1990.
• "Comparison of mixed analog-digital simulators" (with P.E. Allen, B.P. Lum Schu Chan); Proc. Int. Symp. on Circuits and Systems (ISCAS'90), New Orleans, LA, pp.101-104, 1990.
• "Performance evaluation using unbounded Petri nets"; Proc. 3rd Int. Workshop on Petri Nets and Performance Models (PNPM'89), Kyoto, Japan, pp.180-186, 1989.
• "Simulation of mixed, analog-digital circuits with SPICE-like simulators" (with P.E. Allen); Proc. Canadian Conf. on VLSI (CCVLSI'89), Vancouver, B.C., pp.65-72, 1989.
• "Table-driven elements in SPICE-like simulation programs" (with M.S. Zuberek); Proc. 23-rd Asilomar Conf. on Signals, Systems and Computers, Pacific Grove, CA, pp.440-444, 1989.
• "Mixed-mode simulation with SPICE-like circuit simulators''; Proc. 23-rd Asilomar Conf. on Signals, Systems and Computers, Pacific Grove, CA, pp.445-449, 1989.
• "Distributed transmission lines and time-domain analysis in SPICE-like circuit simulators" (with A. Konczykowska, H. Wang); Proc. Int. Symp. on Circuits and Systems (ISCAS'89), Portland, OR, pp.709-712, 1989.
• "Dynamic control of time-domain analysis in the SPICE-PAC simulation package"; Proc. 22-nd Asilomar Conf. on Signals, Systems and Computers, Pacific Grove, CA, pp.412-416, 1988.
• "Timed Petri net models of queueing systems"; Proc. 7-th Annual Int. Phoenix Conf. on Computers and Communications (PCCC'88), Scottsdale, AZ, pp.324-329, 1988.
• "On generation of state space for timed Petri nets"; Proc. 16-th ACM Computer Science Conf. (CSC'88), Atlanta, GA, pp.239-248, 1988.
• "D-timed Petri nets and modelling of timeouts and protocols"; Transactions of the Society for Computer Simulation, vol.4, no.4, pp.331-357, 1987.
• "Interpolation methods in modelling semiconductor devices by enhanced controlled sources"; Proc. 21-st Asilomar Conf. on Signals, Systems and Computers, Pacific Grove, CA, pp.515-519, 1987.
• "Timed Petri nets in modelling and evaluation of multiprocessor systems"; Proc. Int. Conf. on Parallel Processing, St. Charles, IL, pp.695-698, 1987.
• "Parameterized subcircuits in the SPICE-PAC package of simulation subroutines"; Proc. Canadian Conf. on VLSI (CCVLSI'87), Winnipeg, Canada, pp.117-122, 1987.
• "Circuit decompilation in the SPICE-PAC package of simulation subroutines"; Proc. VLSI and Computers - First Int. Conf. on Computer Technology, Systems and Applications (COMPEURO'87), Hamburg, Germany, pp.229-232, 1987.
• "Preemptive D-timed Petri nets, timeouts, modelling and analysis of communication protocols"; Proc. IEEE Sixth Annual Conf. on Global Networks (INFOCOM'87), San Francisco, CA, pp.721-730, 1987.
• "Modified M-timed Petri nets in modelling and performance evaluation of systems"; Proc. ACM 15-th Annual Computer Science Conf. (CSC'87), St. Louis, MO, pp.261-268, 1987.
• "M-timed Petri nets, priorities, preemptions, and performance evaluation of systems"; in Advances in Petri Nets 1985 (Lecture Notes in Computer Science 222), pp.478-498, Springer Verlag 1986.
• "Modified D-timed Petri nets, timeouts, and modelling of communication protocols"; Proc. 6-th Int. Conf. on Distributed Computer Systems, Cambridge, MA, pp.452-457, 1986.
• "M-timed Petri nets and Markov chains in modelling of computer systems"; Proc. 14-th ACM Computer Science Conf. (CSC'86), Cincinnati, OH, pp.101-106, 1986.
• "Inhibitor D-timed Petri nets and performance analysis of communication protocols"; INFOR Journal - Special Issue on Communication System Performance, vol.24, no.3, pp.231-249, 1986.
• "Augmented M-timed Petri nets, modeling and performance evaluation of computer systems"; Transactions of the Society for Computer Simulation, vol.2, no.2, pp.135-153, 1985.
• "Extended D-timed Petri nets, timeouts, and analysis of communications protocols"; Proc. 1985 ACM Annual Conference, Denver, CO, pp.10-15, 1985.
• "Indirect communication, hierarchical structuring, and interfacing circuit simulation with optimization packages"; Proc. 1985 Canadian Conf. on Very Large Scale Integration (CCVLSI'85), Toronto, Canada, pp.196-199, 1985.
• "Performance evaluation using extended timed Petri nets"; Proc. Int. Workshop on Timed Petri Nets, Torino, Italy, pp.272-278, 1985.
• "Generalized M-timed Petri nets and performance evaluation of computer systems"; INFOR Journal - Special Issue on Computer Systems Performance Evaluation, vol.23, no.3, pp.344-362, 1985.
• "Interfacing interactive circuit simulation with standard graphics facilities" (with P. Gillard); Proc. Graphics Interface 85, Montreal, Canada, pp.37-43, 1985.
• "Performance evaluation of concurrent systems using timed Petri nets"; Proc. 13-th ACM Computer Science Conf. (CSC'85), New Orleans, LA, pp.326-329, 1985.
• "A minimax approach to the best mechanical alignment problem" (with J.W. Bandler, M.A. El-Kady, W. Kellermann); ASME Journal of Mechanisms, Transmissions and Automation in Design, vol.106, no.1, pp.31-40, 1984.
• "SPICE-PAC, a package of subroutines for interactive simulation and optimization of circuits"; Proc. IEEE Int. Conf. on Computer Design (ICCD'84), Port Chester, NY, pp.492-496, 1984.
• "SPICE-PAC and libraries of standard modules"; Proc. 1984 Canadian Conf. on Very Large Scale Integration (CCVLSI'84), Edmonton, Canada, 1984.
• "SPICE-PAC subroutines for circuit design" (with M.A. Styblinski); VLSI Systems Design, vol.4, no.10, pp.82-83, 1983.
• "A comparison of recently implemented optimization techniques" (with J.W. Bandler, W. Kellermann); Proc. European Conf. on Circuit Theory and Design (ECCTD'83), Stuttgart, Germany, pp.466-470, 1983.
• "An optimization approach to the best alignment of manufactured and operating systems" (with J.W. Bandler, M.A. El-Kady, W. Kellermann); Proc. Int. Symp. on Circuits and Systems (ISCAS'83), Newport Beach, CA, pp.542-545, 1983.
• "Application of timed Petri nets to analysis of multiprocessor realizations of digital filters"; Proc. 25-th Midwest Symp. on Circuits and Systems, Houghton, MI, August 1982, pp.134-139.
• "Analysis of Le Lann's distributed control protocol by Petri nets"; Proc. 2-nd European Workshop on Theory and Applications of Petri Nets (EWTAPN'81), Bad Honnef, Germany, pp.555-568, 1981.
• "Timed Petri nets and preliminary performance evaluation"; Proc. 7-th Annual Symp. on Computer Architecture, La Baule, France, pp.89-96, 1980.

• "Petri nets and timed Petri nets - basic concepts and properties" (Lecture Notes for CS-6726); Technical Report #2000-01, Department of Computer Science, Memorial University, 20pp., September 2000.
• "Modeling with timed Petri nets - event-driven simulation"; Technical Report #9602, Department of Computer Science, Memorial University, 20pp., September 1996.
• "Modeling with timed Petri nets - model description and representation"; Technical Report #9601, Department of Computer Science, Memorial University, 17pp., August 1996.
• "Application of timed Petri nets to modeling and analysis of flexible manufacturing cells"; Technical Report #9503, Department of Computer Science, Memorial University, 27pp., June 1995.
• "Symbolic analysis in parameter extraction; its implementation and performance" (with A. Konczykowska); Technical Report #9405, Department of Computer Science, Memorial University, St. John's NF, Canada A1B 3X5, November 1994.
• "FIT-S, a simulation-based data-driven parameter extraction program" (with A. Konczykowska); Technical Report #9402, Department of Computer Science, Memorial University, St. John's NF, Canada A1B 3X5, May 1994.
• "FIT-2, a simulation-based parameter extraction program" (with A. Konczykowska); Technical Report #9111, Department of Computer Science, Memorial University of Newfoundland, St. John's NF, Canada A1B 3X5, September 1991.
• "Run-time control of the DC Transfer Curve analysis in the SPICE-PAC simulation package"; Technical Report #9109, Department of Computer Science, Memorial University of Newfoundland, St. John's NF, Canada A1B 3X5, 1991.
• "Comparison of mixed analog-digital simulators" (with P.E. Allen, B.P. Lum Schu Chan); Technical Report #90-01, School of Electrical Engineering, Georgia Institute of Technology, Atlanta, GA 30332, 1990.

Revised: November 12, 2005.