Proc. 7-th Annual Symposium on Computer Architecture, La Baule, France, 6-8 May 1980, pp.89-96.
It is shown that the behavior of a certain class of timed Petri nets can be represented vy a finite labaled directed graph in which the labels describe the probabilities of transitions between vertices of the graph. Further analysis of such a graph can be done by techniques known for Markov chains. The method is applied to evaluation of some performance indices for two simple processor architectures. The timed Petri nets modeling tje processors are shown and the resulting performance indices are compared. Some other architectures are discussed shortly.
Timed petri nets, state graphs, Markov chains, performance evaluation.