Performance limitations of block-multithreaded distributed-memory systems

Zuberek, W.M.

Proc. 2009 Winter Simulation Conference - Modeling Methodology Track, M. D. Rossetti, R. R. Hill, B. Johansson, A. Dunkin, and R. G. Ingalls, eds., Austin, Texas, December 13-16, 2009, pp.899-907 (ISBN 978-1-4244-5171-7).


The performance of modern computer systems is increasingly often limited by long latencies of accesses to the memory subsystems. Instruction-level multithreading is an architectural approach to tolerating such long latencies by switching instruction threads rather than waiting for the completion of memory operations. The paper studies performance limitations in distributed-memory block multithreaded systems and determines conditions for such systems to be balanced. Event-driven simulation of a timed Petri net model of a simple distributed-memory system confirms the derived performance results.


Instruction-level multithreading, block multithreading, distributing-memory systems, performance analysis, performance balancing, timed Petri nets, event-driven simulation.

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