Performance-equivalent multiprocessor systems

Zuberek, W.M.

Proc. ICALP'03 Workshop on Stochastic Petri Nets and Related Formalisms; Eindhoven, The Netherlands, 28-29 June 2003, pp.123-136.

Abstract:

Distributed-memory multiprocessor systems, executing transaction-processing-like jobs, are studied in this paper. The utilization of processors as a function of basic system parameters, such as the computation-to-communication ratio and the number of available jobs, is used as the performance measure. It is shown that systems with different topologies and different numbers of processors are equivalent with respect to their performance if the values of their critical parameters satisfy certain relations. Such equivalence can be used to simplify the simulation-based performance evaluation by analyzing systems which are equivalent with respect to performance to the original ones, but are significantly simpler.

Keywords:

Distributed-memory architectures, performance analysis, performance equivalence, computation-to-communication ratio, event-driven simulation.

References:

• Anderson, T., O. Culler, and D. Patterson, "A case for NOW (Network of Workstations)", IEEE Micro, vol.15, pp.54-64, 1995.
• Bagchi, K.K., A.F. Nielsen, and O. Olsen, O., "Simulation of multicomputer networks", in "Simulation Systems", Zobrist, G.W., Leonard, J.V. (eds), Gordon and Beach, pp.166-201, 2000.
• Baker, M., and R. Buyya, "Cluster computing: the commodity supercomputer"; Software Practice and Experience, vol.19, pp.551-576, 1999.
• Buyya, R., High performance cluster computing: systems and architectures, Prentice-Hall 1999.
• Hwang, K., Advanced computer architecture -- parallelism, scalability, programmability, McGraw-Hill 1993.
• Jain, R., The art of computer systems performance analysis, J. Wiley & Sons 1991.
• Phister, G., In search of clusters, Prentice-Hall 1998.
• Piernas, J., A. Flores, and J.M. Garcia, "Analyzing the performance of MPI in a cluster of workstations based on Fast Ethernet", in "Recent Advances in Parallel Virtual Machine and Message Passing Interface" (LNCSS 1332), Springer-Verlag, pp.17-24, 1997.
• Reisig, W., Petri nets - an introduction (EATCS Monographs on Theoretical Computer Science 4), Springer-Verlag 1985.
• Wang, J., Timed Petri nets - theory and application, Kluwer Academic Publ. 1998.
• Wilkinson, B., Computer architecture - design and performance, Prentice Hall 1996.
• Xu, Z., and K. Hwang, "Modeling communication overhead: MPI and MPL performance on the IBM SP2", IEEE Parallel and Distributed Technology, vol.29, pp.9-23, 1996.
• Zuberek, W.M., "Timed Petri nets - definitions, properties and applications", Microelectronics and Reliability, vol.31, pp.627-644, 1991.
• Zuberek, W.M., "Modeling using timed Petri nets - event-driven simulation", Technical Report #9602, Department of Computer Science, Memorial University, St.John's, Canada A1B 3X5, 1996.
• Zuberek, W.M., "Performance modeling of multithreaded distributed memory architectures", Proc. 2-nd Workshop on Hardware Design and Petri Nets, Williamsburg, VA, pp.63-82, 1999.
• Zuberek, W.M., "Approximate simulation of distributed-memory multithreaded multiprocessors", Proc. 35-th Annual Simulation Symposium, San Diego, CA, pp.107-114, 2002.

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