Department of Computer Science Course: CS 3725

Examples - the VAX 3500 and the MIPS R2000

Both the VAX 3500 and the MIPS R2000 processors have interesting cache structures. The VAX 3500 has two levels of cache memory -- a 1 Kbyte 2-way set associative cache is built into the processor chip itself, and there is an external 64 Kbyte direct mapped cache. The overall cache hit rate is typically 95 to 99%. If there is an on-chip (first level) cache hit, the external memory bus is not used by the processor. The first level cache responds to a read in one machine cycle (90ns), while the second level cache responds within two cycles. Both caches can be configured as caches for instructions only, for data only, or for both instructions and data. In a single processor system, a mixed cache is typical; in systems with several processors and shared memory, one way of ensuring data consistency is to cache only instructions (which are not modified); then all data must come from main memory, and consequently whenever a processor reads a data word, it gets the current value.

The behaviour of a two-level cache is quite interesting; the second level cache does not ``see'' the high memory locality typical of a single level cache; the first level cache tends to strip away much of this locality. The second level cache therefore has a lower hit rate than would be expected from an equivalent single level cache, but the overall performance of the two-level system is higher than using only a single level cache. In fact, if we know the hit rates for the two caches, we can calculate the overall hit rate as , where H is the overall hit rate, and and are the hit rates for the first and second level caches, respectively. DEC claims that the hit rate for the second level cache is about 85%, and the first level cache has a hit rate of over 80%, so we would expect the overall hit rate to be about .

The MIPS R2000 has no on-chip cache, but it has provision for the addition for up to 64 Kbytes of instruction cache and 64 Kbytes of data cache. Both caches are direct mapped. Separation of the instruction and data caches is becoming more common in processor systems, especially for direct mapped caches. In general, instructions tend to be clustered in memory, and data also tend to be clustered, so having separate caches reduces cache conflicts. This is particularly important for direct mapped caches. Also, instruction caches do not need any provision for writing information back into memory.

Both processors employ a write-through policy for memory writes, and both provide some buffering between the cache and memory, so processing can continue during memory writes. The VAX 3500 provides a quadword buffer, while the buffer for the MIPS R2000 depends on the particular system in which it is used. A small write buffer is normally adequate, however, since writes are relatively much less frequent than reads.