Department of Computer Science Course: CS 3725

The 8088 external architecture - pin functions:

The 8088 microprocessor is contained in a 40 pin IC (a standard 40 pin dual in-line package, DIP). Each of these pins is assigned a number (1 to 40, anticlockwise from pin 1) and a label. Pin 1 is normally indicated by a dot in the package. The ``pinouts'' (pin numbers and labels) are shown on the data sheet, together with the fubction of each pin. The following describes the function of some important sets of pins.

Two important connections are power (+5V) and ground, to pins 40 and 20 respectively. Also, some timing device, usually an I8284 clock chip must be connected to the CLK input(pins 19).

The memory address, a full 20 bits, is available on pins , (pins 16 to 9), (pins 8 to 2), and (pins 39 to 35). Address lines are valid for the whole CPU cycle in progress. The low order byte, however, shares its output with the data inputs or outputs, and the high order 4 bits share its outputs with status information. The memory address appears first, and then these pins are used to input or output data or status information. (This multiple use of a set of pins is called ``time multiplexing''). Note that we must have the full address available, in order to obtain data or instructions from memory; therefore we must retain, or ``latch'', the low byte of memory during the time it is available on pins , and the high order 4 bits on lines .

To help in ``capturing'' or latching the low order address byte and the high order 4 bits, another output is available. This is the ALE (Address Latch Enable) output, used to ``strobe'' the address into an address latch. The falling edge of the ALE output occurs at a time when the address is stable on , and can be latched in an external register (say, a set of 8 D flip flops) at this instant.

There are three very useful control pins, namely, (pin 28), (pin 32) and (pin 29). indicates whether the CPU is addressing a memory device or an I/O device. When is at logic 1, an I/O device is currently being accessed. This is the only output which distinguishes between I/O and memory operations.

is a ``strobe'' output, which indicates to external devices that the CPU wishes to input data from memory or an I/O device. When is at logic 0, the CPU expects data to be placed on the data bus; this data must be stable when makes a 0-1 transition.

is a strobe output which indicates to external devices that the CPU wishes to output a byte of data to a memory location or an I/O device. When WR is at logic 0, it is guaranteed that the data output on the data bus is stable, and should be captured by memory or an output device. Note that when the CPU is operating at its maximum speed, the and strobe outputs have a duration of about 320 ns. This is all the time available for memory or an output device to capture output data, or for memory or an input device to present stable data to the data bus of the CPU.