Department of Computer Science Course: CS 3725

An example I/O system for the IBM PC

Figure  shows the processor and bus structure of the INTEL 8088 processor used in the IBM PC. The original PC had a number of other peripheral devices which we will also make use of, and the bus structure shown is not the full bus structure used in the PC.

  
Figure: The 8088 processor with a fully functional bus structure

The PC had an internal bus called the ISA bus, with 20 address lines and 8 data lines (this was extended in the IBM PC/AT bus to 24 address lines and 16 data lines.) This bus was the interface through which peripheral devices were added to the PC, and became a de facto standard bus in the industry. In fact, several of the MIPS R2000 processors had ISA bus slots, to allow the use of the cheaper PC peripheral devices.

The ISA bus is shown in Figure  shows the processor and bus structure of the ISA bus, with the extension (the C and D slots) used in the IBM PC/AT. This extension allowed a 16 bit word, and 24 address lines, and supported the more advanced I80286 processor.

  
Figure: The ISA bus structure, with the IBM PC/AT extensions

We will consider the design of a simple data acquisition system for an ISA bus system based on the INTEL 80x8x processor which collects a word of data at regular intervals (determined by a clock signal) and which places those data words in a list. For simplicity, let us assume that the clock signal is used to initiate the start of the data collection, and that the data collector produces a signal done when the data word is available to be sent to the processor. (A ``real'' device with this behaviour might be an analog to digital converter, which takes a voltage as input and produces a number proportional to the voltage as output.)

We will design the system for program-controlled I/O, then modify it for interrupt controlled I/O. (We could also develop a DMA system for the device, but it is ``overkill'' for this simple application.) To implement a general system, we need to add an interrupt mechanism to our basic processor; the original IBM PC used the I8259 programmable interrupt controller. (Actually, the PC-AT used two such controllers, and the 16 interrupt inputs so provided are still part of the AT bus, generally called the ISA bus. The primary controller had port addresses and , and the secondary, which was attached to IR2 of the primary, had port addresses - .) We will assume that there are interrupts available on the ISA bus.

We will also add a timer (we will use the I8254 programmable interval timer, which is functionally equivalent to the I8253 used in the original PC. This device contains three separate timers, each of which is independently programmable, and which can operate in any of five different modes. Here, the timer on the original PC is not really available; timer channel 0 is used as the system timer interrupt, timer channel 1 generates the DRAM refresh request, and timer channel 2 generates the internal speaker tone. (The timer control registers were mapped as port addresses - , although only 4 addresses are actually required for the device.)

We will also add an input port and an output port. (For this, we will use another ``programmable'' device, also found on the original PC; the 8255 programmable peripheral interface.) This device has 3 ports, individually configurable as input and output. It operates in several modes, and in one of those modes, the individual bits in one port (Port C) can be separately configured for input or output, and set or reset individually. This feature makes the bits in Port C ideal for implementing the handshake signals.

The final device we will add is an analog-to-digital converter. There are many such devices available, with a wide range of speed and accuracy. Generally, high speed and high accuracy imply a high price, while relaxing constraints on either speed or accuracy dramatically reduce the cost. Accuracy is generally expressed in bits, with an 8-bit accuracy (1 part in 256) device with a conversion time of 50 s. available for less than $5.00, and a 16 bit device with a similar conversion time costs over 10 times that amount.

Since cost is not a consideration for a paper design, we will use a device with 16 bit accuracy, and a conversion time of 10 s., the ADS7805 from Burr-Brown. A data sheet is available at url http://www.burr-brown.com/products/catalog/datasheets/ADS7805.html This device has excellent linearity, and reasonable speed at a relatively low cost.

The original PC had a set of I/O port addresses reserved for user-built devices, the addresses in the range - , or - .

We will add our devices at the addresses as follows:

device address (hex) address (decimal) Comment

ADS7805 may not use all

I8254 timer maps to 4 devices

I8255 PPI maps to 4 devices

We can ``drive'' the ADC from the timer and the PPI, or from the address lines on the computer itself.

First, we will look at some of the details of the timing of the 80x8x bus.