Department of Computer Science Course: CS 3725

Input-Output Architecture

In our discussion of the memory hierarchy, it was implicitly assumed that memory in the computer system would be ``fast enough'' to match the speed of the processor (at least for the highest elements in the memory hierarchy) and that no special consideration need be given about how long it would take for a word to be transferred from memory to the processor -- an address would be generated by the processor, and after some fixed time interval, the memory system would provide the required information. (In the case of a cache miss, the time interval would be longer, but generally still fixed. For a page fault, the processor would be interrupted; and the page fault handling software invoked.)

Although input-output devices are ``mapped'' to appear like memory devices in many computer systems, I/O devices have characteristics quite different from memory devices, and often pose special problems for computer systems. This is principally for two reasons:

• I/O devices span a wide range of speeds. (e.g. terminals accepting input at a few characters per second; disks reading data at over 10 million characters / second).
• Unlike memory operations, I/O operations and the CPU are not generally synchronized with each other.

Figure  shows the general I/O structure associated with many medium-scale processors. Note that the I/O controllers and main memory are connected to the main system bus. The cache memory (usually found on-chip with the CPU) has a direct connection to the processor, as well as to the system bus.

  
Figure: A general I/O structure for a medium-scale processor system

Note that the I/O devices shown here are not connected directly to the system bus, they interface with another device called an I/O controller. In simpler systems, the CPU may also serve as the I/O controller, but in systems where throughput and performance are important, I/O operations are generally handled outside the processor.

Until relatively recently, the I/O performance of a system was somewhat of an afterthought for systems designers. The reduced cost of high-performance disks, permitting the proliferation of virtual memory systems, and the dramatic reduction in the cost of high-quality video display devices, have meant that designers must pay much more attention to this aspect to ensure adequate performance in the overall system.

Because of the different speeds and data requirements of I/O devices, different I/O strategies may be useful, depending on the type of I/O device which is connected to the computer. Because the I/O devices are not synchronized with the CPU, some information must be exchanged between the CPU and the device to ensure that the data is received reliably. This interaction between the CPU and an I/O device is usually referred to as ``handshaking''. For a complete ``handshake,'' four events are important:

• The device providing the data (the talker) must indicate that valid data is now available.
• The device accepting the data (the listener) must indicate that it has accepted the data. This signal informs the talker that it need not maintain this data word on the data bus any longer.
• The talker indicates that the data on the bus is no longer valid, and removes the data from the bus. The talker may then set up new data on the data bus.
• The listener indicates that it is not now accepting any data on the data bus. the listener may use data previously accepted during this time, while it is waiting for more data to become valid on the bus.

Note that each of the talker and listener supply two signals. The talker supplies a signal (say, data valid, or DAV) at step (1). It supplies another signal (say, data not valid, or ) at step (3). Both these signals can be coded as a single binary value (DAV) which takes the value 1 at step (1) and 0 at step (3). The listener supplies a signal (say, data accepted, or DAC) at step (2). It supplies a signal (say, data not now accepted, or ) at step (4). It, too, can be coded as a single binary variable, DAC. Because only two binary variables are required, the handshaking information can be communicated over two wires, and the form of handshaking described above is called a two wire Handshake. Other forms of handshaking are used in more complex situations; for example, where there may be more than one controller on the bus, or where the communication is among several devices. Figure  shows a timing diagram for the signals DAV and DAC which identifies the timing of the four events described previously.

  
Figure: Timing diagram for two-wire handshake

Either the CPU or the I/O device can act as the talker or the listener. In fact, the CPU may act as a talker at one time and a listener at another. For example, when communicating with a terminal screen (an output device) the CPU acts as a talker, but when communicating with a terminal keyboard (an input device) the CPU acts as a listener.