Department of Computer Science Course: CS 3724

Sequential Logic

Sequential logic differs from combinational logic in that the output of the logic device is dependent not only on the present inputs to the device, but also on past inputs; i.e., the output of a sequential logic device depends on its present internal state and the present inputs. This implies that a sequential logic device has some kind of memory of at least part of its ``history'' (i.e., its previous inputs).

A simple memory device can be constructed from combinational devices with which we are already familiar. By a memory device, we mean a device which can remember if a signal of logic level 0 or 1 has been connected to one of its inputs, and can make this fact available at an output. A very simple, but still useful, memory device can be constructed from a simple OR gate, as shown in Figure 2.1.

Figure 2.1:

In this memory device, if A and Q are initially at logic 0, then Q remains at logic 0. However if the single input A ever becomes a logic 1, then the output Q will be logic 1 ever after, regardless of any further changes in the input at A. In this simple memory, the output is a function of the state of the memory element only; after the memory is ``written'' then it cannot be changed back. However, it can be ``read.'' Such a device could be used as a simple read only memory, which could be ``programmed'' only once. Often a state table or timing diagram is used to describe the behaviour of a sequential device. Figure 2.2 shows both a state table and a timing diagram for this simple memory. The state table shows the state which the device enters after an input (the ``next state''), for all possible states and inputs. For this device, the output is the value stored in the memory.

Figure 2.2:

Note that the output of the memory is used as one of the inputs; this is called feedback and is characteristic of programmable memory devices. (Without feedback, a ``permanent'' electronic memory device would not be possible.) The use of feedback in a device can introduce problems which are not found in strictly combinational circuits. In particular, it is possible to inadvertently construct devices for which the output is not determined by the inputs, and for which it is not possible to predict the output. A simple example is an inverter with its input connected to its output. Such a device is logically inconsistent; in a physical implementation the device would probably either oscillate from 1 to 0 to 1 $\cdots$ or remain at an intermediate value between logic 0 and logic 1, producing an invalid and erroneous output.

More complicated, stable, memory elements could be constructed using simple logic gates. In particular, simple, alterable memory cells can be readily constructed. One basic (but not often used in this form) memory device is the following, called an RS (reset-set) latch, or flip flop. It is the most basic of all the class of circuits which are called latches or flip flops. A logic diagram for this device is shown in Figure 2.3, together with its circuit symbol.

We can analyze the circuit shown in Figure 2.3 in a straightforward manner, to determine the outputs $\overline{Q}$ and $Q$ for various inputs to R and S; e.g., suppose we raise S to logic 1, with $Q$ at logic 0. Then $\overline{Q}$ must be 0, (the output of a NOR gate is 0 if any input is 1), and $Q$ must be 1. If S is returned to 0, then $\overline{Q}$ remains 0 and $Q$ remains 1; i.e., the RS latch ``remember'' if S was set to 1, while R is 0. If R is raised to logic 1 while S is at logic 0, then $Q$ is set to logic 0, and $\overline{Q}$ is set to logic 1; i.e., the latch is reset. If both R and S are raised to logic 1, then both $Q$ and $\overline{Q}$ will be at logic 0. This output is inconsistent with the identification of $Q$ and $\overline{Q}$ as the two outputs, and therefore this combination of inputs for R and S should be avoided.

A more serious problem occurs if R and S change from logic 1 to logic 0 simultaneously. This situation is called a race condition. If both R and S are at logic 1, then $Q$ and $\overline{Q}$ are at logic 0. When R and S are both set to 0, then both $Q$ and $\overline{Q}$ should switch to logic 1. However, when they switch to logic 1, they should cause a switch back to logic 0 again, because if the logic 1 input to each NOR gate. If both NOR gates were identical, this would occur over and over again, indefinitely -- an oscillation of the outputs $Q$ and $\overline{Q}$ from state 0 to 1 and back, with a period depending on the time delay for the NOR gate. In practice, one gate is a little faster than the other, and the final outcome depends on the relative speeds of the two gates. other. However, the final outcome cannot be predicted.

A state table for the RS flip flop is shown in Figure 2.3, together with its a logic diagram and its circuit symbol. (The circuit symbol for a flip flop or latch is a rectangular block, with the inputs on the left and outputs on the right. Special inputs may be on the top and bottom.)

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Figure 2.3:

There are three control signals often associated with flip flops; they are the clock or enable signal; the preset, and the clear signal. The clock signal is ANDed with the inputs R and S, so that these signals can reach the flip-flop only when the clock pulse is 1; all other times the inputs to the inputs to the flip-flop are 0, and it retains its previous value.

The clock input is used for several purposes; it is used to ``capture'' data which is available for only a short time; and it is used to synchronize several flip-flops so they can all operate simultaneously, or synchronously. Figure 2.4 (a) shows a circuit diagram for a clocked RS flip-flop, together with its circuit symbol in Figure 2.4 (b). Note the special symbol, similar to an arrowhead, which denotes the clock input.

Figure 2.4:

The preset and clear signals are used to set the state of the flip-flop regardless of the state of the clock input. Because they are not synchronized by the clock pulse, they are said to be asynchronous. Figure 2.5 shows how a simple clocked RS flip flop with preset and clear inputs could be constructed from simple logic gates.

Figure 2.5:

The preset and clear act as an unclocked RS flip-flop, and consequently a logic 1 should not be applied to both at the same time.

A dual form of the RS flip flop, the $\overline{R} \overline{S}$ flip flop can be implemented with NAND gates, as shown in Figure 2.6.

Figure 2.6:

Clock inputs, together with preset and clear inputs could similarly be provided for this device. Since the inputs to this device are inverted, the preset and clear inputs would also be inverted.