This is a list of supported or soon-to-be supported chips, with a guide
to detecting them and peculiarities of each of them.

LM78 (supported)
  This is the basic chip, to which all others are compared.

  Detection: If it is none of the other chips, it is assumed to be a LM78
             0x49:6 == 0, 0x49:7 == 0.


LM78-J (supported)
  Functionally, there is no real difference between the LM78 and LM78-J. 
  It allows an unconditional reset by writing a 1 to 0x49:5.

  Detection: 0x49:6 == 1 for the LM78-J.

  Register changes:
  0x49:6  LM78:   0
          LM78-J: 1
   

LM79 (supported)
  An LM78 with an additional VID line, to correctly identify the core voltage
  for the newer Pentium-class processors.

  Detection: 0x49:7 == 1 for the LM79

  Register changes:
  0x49:0  LM78: undefined
          LM79: VID4 input
  0x49:7  LM78: 0
          LM79: 1


LM80 (supported)
  This chip can only be accessed through the SMBus. It is _not_ compatible
  with the LM78, though it has almost the same functionality. There are no
  VID lines connetions, though, and only 2 FANs. There are some other
  minor differences, too.


W83781D (supported)
  This is a LM78 clone, with some additional features.

  It has no NMI interrupt support. It can't chain LM75 chips (but it emulates
  two of them). It does not have an SMI interrupt reporting pin, or FIFO
  address out-of range reporting. It has 5 VID lines, like the LM79. It
  can set a divisor for FAN3. It can set the clock input speed, and the
  sample speed. 

  It has two additional temperature sensors onboard. They can be accessed
  through the ISA bus (using some additional registers), or through the
  SMBus. In the latter case, they will simulate two LM75 chips, with their
  own SMBus addresses - which makes three SMBus addresses all together.

  It can selectively beep when an input is too low or too high.
 
  Detection: 0x4F == 5CA3
  Note that some tricks must be used to read a word value from a bytesized
  register!

  Register changes:
  0x40:5  LM7x: 0 == IRQ, 1 == NMI interrrupt reporting
          WINB: 0 == IRQ active high, 1 == IRQ active low
  0x41:5  LM7x: 1 == LM75 out of bounds detected
          WINB: 1 == Temperature sensor 2 or 3 interrupt out of bounds detected
  0x42:5  LM7x: 1 == FIFO out of bounds detected
          WINB: undefined
  0x42:6  LM7x: 1 == SMI_IN interrupt detected
          WINB: undefined
  0x43:5  LM7x: 1 == Enable SMI interrupt for LM75
          WINB: 1 == Enable SMI interrupt for temperature sensors 2 and 3
  0x44:5  LM7x: 1 == Enable SMI interrupt for FIFO out of bounds
          WINB: undefined
  0x44:6  LM7x: 1 == Enable SMI interrupt chaining
          WINB: undefined
  0x45:5  LM7x: 1 == Enable IRQ interrupt for LM75
          WINB: 1 == Enable IRQ interrupt for temperature sensors 2 and 3
  0x46:5  LM7x: 1 == Enable IRQ interrupt for FIFO out of bounds
          WINB: undefined
  0x46:6  LM7x: 1 == Enable IRQ interrupt chaining
          WINB: undefined
  0x49:0  LM78: undefined
          WINB: VID4 input (like LM79)
  0x49:5  LM78: Reset
          WINB: undefined
  0x49:6  LM78: 0 (LM78-J: 1)
          WINB: 0
  0x49:7  LM78: 0 (LM79: 1)
          WINB: 0

  0x4A-0x5F: New WINB registers (undefined for LM7x)
  

LM75 (supported)
  A temperature sensor chip, which only operates over the SMBus. Several
  LM75 chips can be chained and connected to an LM78. Note that the
  Winbond W83781D emulates two LM75 chips, and real LM75 chips can not be
  chained to it.
